ZH,(.RTSM_VE_AEMv8A arm,rtsm_ve,aemv8aarm,vexpress"1chosenaliases/=/smb/motherboard/iofpga@3,00000000/uart@090000/E/smb/motherboard/iofpga@3,00000000/uart@0a0000/M/smb/motherboard/iofpga@3,00000000/uart@0b0000/U/smb/motherboard/iofpga@3,00000000/uart@0c0000cpus"1cpu@0]cpu arm,armv8i mspin-table{cpu@1]cpu arm,armv8i mspin-table{cpu@2]cpu arm,armv8i mspin-table{cpu@3]cpu arm,armv8i mspin-table{memory@80000000]memory iinterrupt-controller@2c001000%arm,cortex-a15-gicarm,cortex-a9-gic"@i,, ,@ ,`   timerarm,armv8-timer0   pmuarm,armv8-pmuv30<=>?smb simple-bus"1x  ?            !!""##$$%%&&''(())**motherboardrs1arm,vexpress,v2m-p1simple-bus"1flash@0,00000000arm,vexpress-flashcfi-flashivram@2,00000000arm,vexpress-vram iethernet@2,02000000smsc,lan91c111 iclk24mhz fixed-clock!n6 .v2m:clk24mhzrefclk1mhz fixed-clock!B@.v2m:refclk1mhzrefclk32khz fixed-clock!.v2m:refclk32khziofpga@3,00000000arm,amba-bussimple-bus"1 sysreg@010000arm,vexpress-sysregiAQsysctl@020000arm,sp810arm,primecelli ]drefclktimclkapb_pclk!0.timerclken0timerclken1timerclken2timerclken3aaci@040000arm,pl041arm,primecelli ] dapb_pclkmmci@050000arm,pl180arm,primecelli  p y]dmclkapb_pclkkmi@060000arm,pl050arm,primecelli ]dKMIREFCLKapb_pclkkmi@070000arm,pl050arm,primecelli ]dKMIREFCLKapb_pclkuart@090000arm,pl011arm,primecelli ]duartclkapb_pclkuart@0a0000arm,pl011arm,primecelli ]duartclkapb_pclkuart@0b0000arm,pl011arm,primecelli ]duartclkapb_pclkuart@0c0000arm,pl011arm,primecelli ]duartclkapb_pclkwdt@0f0000arm,sp805arm,primecelli]dwdogclkapb_pclktimer@110000arm,sp804arm,primecelli]dtimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecelli]dtimclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecelli] dapb_pclkclcd@1f0000arm,pl111arm,primecelli]dclcdclkapb_pclkvirtio_block@0130000 virtio,mmioi*fixedregulator@0regulator-fixed3V32Z2Zmccarm,vexpress,config-busosc@1arm,vexpress-osc #jep! .v2m:oscclk1reset@0arm,vexpress-reset muxfpga@0arm,vexpress-muxfpga shutdown@0arm,vexpress-shutdown reboot@0arm,vexpress-reboot dvimode@0arm,vexpress-dvimode  modelcompatibleinterrupt-parent#address-cells#size-cellsserial0serial1serial2serial3device_typeregenable-methodcpu-release-addr#interrupt-cellsinterrupt-controllerinterruptslinux,phandleclock-frequencyrangesinterrupt-map-maskinterrupt-maparm,v2m-memory-mapbank-width#clock-cellsclock-output-namesgpio-controller#gpio-cellsclocksclock-namescd-gpioswp-gpiosmax-frequencyvmmc-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-range